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100341 Low Power 8-Bit Shift Register
July 1988 Revised August 2000
100341 Low Power 8-Bit Shift Register
General Description
The 100341 contains eight edge-triggered, D-type flip-flops with individual inputs (Pn) and outputs (Qn) for parallel operation, and with serial inputs (Dn) and steering logic for bidirectional shifting. The flip-flops accept input data a setup time before the positive-going transition of the clock pulse and their outputs respond a propagation delay after this rising clock edge. The circuit operating mode is determined by the Select inputs S0 and S1, which are internally decoded to select either "parallel entry", "hold", "shift left" or "shift right" as described in the Truth Table. All inputs have 50 k pulldown resistors.
Features
s 35% power reduction of the 100141 s 2000V ESD protection s Pin/function compatible with 100141 s Voltage compensated operating range = -4.2V to -5.7V s Available to industrial grade temperature range
Ordering Code:
Order Number 10034SC 100341PC 100341QI 100341QC Package Number M24B N24E V28A V28A Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (-40C to +85C)
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagrams
24-Pin DIP/SOIC
Pin Descriptions
Pin Names CP S0 , S1 D0 , D7 P0-P7 Q0-Q7 Description Clock Input Select Inputs Serial Inputs Parallel Inputs Data Outputs 28-Pin PLCC
(c) 2000 Fairchild Semiconductor Corporation
DS009880
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100341
Truth Table
Function Load Register Shift Left Shift Left Shift Right Shift Right Hold Hold Hold
H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW-to-HIGH Transition
Inputs D7 X X X L H X X X D0 X L H X X X X X S1 L L L H H H X X S0 L H H L L H X X CP
Outputs

X L H
Q7 P7 Q6 Q6 L H
Q6 P6 Q5 Q5 Q7 Q7
Q5 P5 Q4 Q4 Q6 Q6
Q4 P4 Q3 Q3 Q5 Q5
Q3 P3 Q2 Q2 Q4 Q4
Q2 P2 Q1 Q1 Q3 Q3
Q1 P1 Q0 Q0 Q2 Q2
Q0 P0 L H Q1 Q1
No Change
Logic Diagram
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100341
Absolute Maximum Ratings(Note 1)
Storage Temperature (TSTG) Maximum Junction Temperature (TJ) VEE Pin Potential to Ground Pin Input Voltage (DC) Output Current (DC Output HIGH) ESD (Note 2)
-65C to +150C +150C -7.0V to +0.5V
VEE to +0.5V
Recommended Operating Conditions
Case Temperature (TC) Commercial Industrial Supply Voltage (VEE) 0C to +85C
-40C to +85C -5.7V to -4.2V
-50 mA 2000V
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Commercial Version DC Electrical Characteristics
Symbol VOH VOL VOHC VOLC VIH VIL IIL IIH IEE Parameter Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current Power Supply Current -157 -167 -75 -75 mA mA -1165 -1830 0.50 240 Min -1025 -1830 -1035 -1610 -870 -1475
(Note 3)
Typ -955 -1705 Max -870 -1620 Units mV mV mV mV mV mV A A VIN = VIH (Max) or VIL (Min) VIN = VIH (Min) or VIL (Max) Guaranteed HIGH Signal for all Inputs Guaranteed LOW Signal for all Inputs VIN = VIL (Min) VIN = VIH (Max) Inputs OPEN VEE = -4.2V to -4.8V VEE = -4.2V to -5.7V Conditions Loading with 50 to -2.0V Loading with 50 to -2.0V
VEE = -4.2V to -5.7V, VCC = VCCA = GND, TC = 0C to +85C
Note 3: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under "worst case" conditions.
DIP AC Electrical Characteristics
VEE = -4.2V to -5.7V, VCC = VCCA = GND Symbol fMAX tPLH tPHL tTLH tTHL tS tH tPW(H) Parameter Max Clock Frequency Propagation Delay CP to Output Transition Time 20% to 80%, 80% to 20% Setup Time Hold Pulse Width HIGH CP Dn, Pn Sn Dn, Pn Sn TC = 0C Min 400 0.90 0.35 0.65 1.60 0.80 0.60 2.00 1.90 1.30 Max TC = +25C Min 400 1.00 0.35 0.65 1.60 0.80 0.60 2.00 2.00 1.30 Max TC = +85C Min 400 1.00 0.35 0.65 1.60 0.80 0.60 2.00 ns Figure 3 ns 2.10 1.30 Max Units MHz ns ns ns Figure 4 Conditions Figures 2, 3 Figures 1, 3 (Note 4) Figures 1, 3
Note 4: The propagation delay specified is for the switching of a single output. Delays may vary up to 0.40 ns if multiple outputs are switching simultaneously.
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100341
Commercial Version (Continued) SOIC and PLCC AC Electrical Characteristics
VEE = -4.2V to -5.7V, VCC = VCCA = GND Symbol fMAX tPLH tPHL tTLH tTHL tS tH tPW(H) tOSHL Parameter Maximum Clock Frequency Propagation Delay CP to Output Transition Time 20% to 80%, 80% to 20% Setup Time Hold Time Pulse Width HIGH CP Dn, Pn Sn Dn, Pn Sn Maximum Skew Common Edge Output-to-Output Variation Clock to Output Path tOSLH Maximum Skew Common Edge Output-to-Output Variation Clock to Output Path tOST Maximum Skew Opposite Edge Output-to-Output Variation Clock to Output Path tps Maximum Skew Pin (Signal) Transition Variation Clock to Output Path
Note 5: The propagation delay specified is for the switching of a single output. Delays may vary up to 0.40 ns if multiple outputs are switching simultaneously. Note 6: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design
TC = 0C Min 425 0.90 0.35 0.55 1.50 0.70 0.50 2.00 200 1.70 1.20 Max
TC = +25C Min 425 1.00 0.35 0.55 1.50 0.70 0.50 2.00 200 1.80 1.20 Max
TC = +85C Min 425 1.00 0.35 0.55 1.50 0.70 0.50 2.00 200 1.90 1.20 Max
Units MHz ns ns ns
Conditions Figures 2, 3 Figures 1, 3 (Note 5) Figures 1, 3
Figure 4 ns ns ps Figure 3 PLCC Only (Note 6) PLCC Only
200
200
200
ps
(Note 6) PLCC Only
250
250
250
ps
(Note 6) PLCC Only
250
250
250
ps
(Note 6)
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Industrial Version PLCC DC Electrical Characteristics
(Note 7)
VEE = -4.2V to -5.7V, VCC = VCCA = GND, TC = -40C to +85C TC = -40C TC = 0C to +85C Symbol Parameter Min Max Min Max VOH VOL VOHC VOLC VIH VIL IIL IIH IEE Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current Power Supply Current -157 -167 -75 -75 -157 -167 -75 -75 mA mA -1170 -1830 0.50 240 -1085 -1830 -1095 -1565 -870 -1480 -1165 -1830 0.50 240 -870 -1575 -1025 -1830 -1035 -1610 -870 -1475 -870 -1620
Units mV mV mV mV mV mV A A VIN = VIH(Max) or VIL (Min) VIN = VIH (Min) or VIL (Max) for all Inputs
Conditions Loading with 50 to -2.0V Loading with 50 to -2.0V
Guaranteed HIGH Signal Guaranteed LOW Signal for all Inputs VIN = VIL (Min) VIN = VIH (Max) Inputs OPEN VEE = -4.2V to -4.8V VEE = -4.2V to -5.7V
Note 7: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under "worst case" conditions.
PLCC AC Electrical Characteristics
VEE = -4.2V to -5.7V, VCC = VCCA = GND Symbol fMAX tPLH tPHL tTLH tTHL tS tH tPW(H) Parameter Max Clock Frequency Propagation Delay CP to Output Transition Time 20% to 80%, 80% to 20% Setup Time Hold Time Pulse Width HIGH Dn, P n Sn Dn, P n Sn CP TC = -40C Min 425 0.90 0.30 0.60 1.70 0.90 0.50 2.00 1.80 1.90 Max TC = +25C Min 425 1.00 0.35 0.55 1.50 0.70 0.50 2.00 1.80 1.20 Max TC = +85C Min 425 1.00 0.35 0.55 1.50 0.70 0.50 2.00 ns Figure 3 ns 1.90 1.20 Max Units MHz ns ns ns Figure 4 Conditions Figures 2, 3 Figures 1, 3 (Note 8) Figures 1, 3
Note 8: The propagation delay specified is for the switching of a single output. Delays may vary up to 0.40 ns if multiple outputs are switching simultaneously.
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100341
Test Circuitry
Note: * * * * * * VCC, VCCA = +2V, VEE = -2.5V L1, L2 and L3 = equal length 50 impedance lines RT = 50 terminator internal to scope Decoupling 0.1 F from GND to VCCand VEE All unused outputs are loaded with 50 to GND CL = Fixture and stray capacitance 3 pF
FIGURE 1. AC Test Circuit
Note: * * * For shift right mode pulse generator connected to S0 is moved to S1. Pulse generator connected to S1 has a LOW frequency 99% duty cycle, which allows occasional parallel load. The feedback path from output to input should be as short as possible.
FIGURE 2. Shift Frequency Test Circuit (Shift Left)
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Switching Waveforms
FIGURE 3. Propagation Delay and Transition Times
Note: tS is the minimum time before the transition of the clock that information must be present at the data input. tH is the minimum time after the transition of the clock that information must remain unchanged at the data input.
FIGURE 4. Setup and Hold Times
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100341
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E
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100341 Low Power 8-Bit Shift Register
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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